1. Field of the Invention
The present invention relates to an ultra-thin copper foil with a carrier foil used at the time of producing a printed wiring board. In particular, the present invention relates to an ultra-thin copper foil with a carrier foil used preferably for producing a printed wiring board for high density ultra-fine wiring or a multilayer printed wiring board.
2. Description of the Related Art
A printed wiring board is produced as mentioned below.
First, after placing a thin copper foil for forming a surface circuit on a surface of an insulative substrate consisting of a glass epoxy resin or a polyimide resin and so on, by heating and laminating, a copper clad laminate is produced.
Next, after placing a through hole and a through hole plating are performed sequentially, an etching process is performed to a copper foil in the surface of the copper clad laminate, a wiring pattern having a desired line width and desired pitches of adjacent lines are formed, and finally, forming of a solder resist and other finishing processes are performed.
In the copper foil used at that time, a surface of the side that is laminated to a substrate is defined as a treatment side, an anchoring effect is exhibited on the substrates by the treatment side to improve the peel strength between the substrate and the copper foil to assure reliability as the printed wiring board.
Further, recently, the treatment side of the copper foil is covered with a resin for bonding such as an epoxy resin, and the copper foil with resin that this resin for bonding is made to an insulating resin layer in semi-cured state (B stage) is used as a copper foil for forming a surface circuit, then a printed wiring board, in particular a build up wiring board is produced by laminating side of the insulating resin layer to substrate.
Moreover, corresponding to high integration of various electronic parts, in such a build-up printed wiring board, density growth is needed for a wiring pattern, and there has been a demand for a printed wiring board with wiring patterns consisting a wiring of fine line widths and pitches of adjacent lines, that is to say, fine patterns. For example, in the case of a printed wiring board used for a semiconductor package, a printed wiring board having a high density ultra-fine wiring of which line widths and pitches of adjacent lines are around 15 mu m respectively has been demanded.
If a thick copper foil is used as a copper foil for a high density ultra-fine wiring board of such a printed wiring board, the time that is necessary for etching until reaching a surface of a substrate becomes longer. As a result, the verticality of the sidewalls of the wiring patterns formed is ruined, an etching factor indicated in the following equation Ef becomes smaller. Ef=2H/(B−T)
H is the thickness of a copper foil, is the bottom width of a formed printed wiring board.
T is the top width of a formed printed wiring board.
These problems are not serious in the case that the line width of wiring in the formed wiring pattern, however, it may lead to disconnection in the case of the wiring pattern of which line width is narrow.
On the contrary, in the case of a thin copper foil, the etching factor Ef can be larger.
Incidentally, peel strength of a conventional copper foil and a substrate assures peel strength by depositing copper grains on the surface of the side bonded with the substrate to be the treatment side and by embedding a protrusion of the copper grains of this copper foil to the substrate. Consequently, until the embedded protrusion of the copper grains is removed completely from the substrate, a copper remains (this phenomenon is usually called as treatment transfer after etching, it may be a cause that insulation failure is occurred in the case that the pitches of adjacent lines of the wiring pattern is narrow. The time for etching-removing this embedded protrusion of the copper grains completely does not greatly affect the wiring pattern, however the etching time affects greatly in the case that the thickness of the copper foil is thin. That is to say, since the etching time to remove the embedded protrusion becomes longer in comparison to the etching time of the copper foil, in the process of etching-removing the embedded protrusion, an etching of side wall of the wiring pattern already formed progresses, as a result, the Ef value becomes smaller.
In the case of using a thin copper foil, in fact, such a problem can be solved if the surface roughness is made smaller, however, in that case, it is difficult to produce the printed wiring board having the reliable and fine wiring pattern, since the peel strength between the copper foil and the substrate becomes smaller.
Moreover, in the case of the thin copper foil, since the mechanical strength is small, wrinkles and creases cause easily, further the copper foil may go out when producing a printed wiring board, therefore there is a problem that the greatest care is required for handling.
As mentioned above, it is considerably difficult to produce a printed wiring board having fine wiring pattern that the Ef value is large and that the peel strength is large as a practical matter. In particular, it is virtually impossible to form the wiring pattern with a high density ultra-fine wiring of which interval of lines or line width is around 15 mu m by using a commercially available copper foil, and in fact, it is strongly desired to develop a copper foil for permitting that.
As such a copper foil used for high density ultra-fine wiring (fine pattern) of which interval of lines or line width is around 15 mu m, a copper foil having the thickness is 9 mu m or leas, in particular 5 mu m or less is suitable.
As such an ultra-thin copper foil used for a fine pattern, the applicant of the present invention discloses the following techniques.
In Japanese Unexamined Patent Publication No. 2000-269637, a copper foil characterized that it is an ultra-thin copper foil with a carrier foil, a copper foil having a surface roughness Rz is 1.5 mu m or less is defined as a carrier foil, on the surface a peeling layer and an electrolytic copper plating layer are laminated in this order, and the surface of the outermost layer of the electrolytic copper plating layer is defined as a treatment side is disclosed.
In Japanese Unexamined Patent Publication No. 331537, a copper foil with a carrier foil is an ultra-thin copper foil wherein a copper foil is defined as a carrier foil, on the surface a peeling layer and an electrolytic copper plating layer are electroplated in this order, and a copper foil with a carrier foil characterized that a portion adjacent to right-and-left edges between the copper foil with a carrier foil and the electrolytic copper plating layer is made to be connected strongly in comparison to a middle portion of them and that the outermost surface of the electrolytic copper plating layer is roughened are disclosed.
In Published Japanese Translation of a PCT Application No. 2003-524078, a copper foil characterized that a carrier foil that is smoothed to make a mat surface roughness Rz is 3.5 mu m or lees is used, on the mat surface a peeling layer and an electrolytic copper plating layer are electroplated in this order, and the outermost surface of the electrolytic copper plating layer is defined as a treatment side is disclosed.
These copper foils with a carrier foil are shown in FIG. 1. The ultra-thin copper foil with a carrier foil has the peeling layer 2 and the electrolytic copper plating layer (copper foil) 4 formed in this order on one side of the copper foil as a carrier 1 (called as the “carrier foil” below), and consists of the treatment side 4a formed by electrodepositing a roughening grain of a copper 5 on the exposed surface (surface) of the electrolytic copper plating layer 4.
Further, after overlapping the treatment side 4a on a glass-epoxy substrate (not illustrated), the whole is laminated, next by peeling/removing the carrier foil 1 the side of junction of the electrolytic copper plating layer and the carrier foil is exposed, the predetermined wiring pattern is formed there.
The carrier foil 1 functions as a reinforcing material (carrier) that back up the thin electrolytic copper plating layer 4 until contacting to the substrate. Further, the peeling layer 2 is a layer for peeling easily when separating the above electrolytic copper plating layer (copper foil) 4 and the carrier foil 1, hence the carrier foil 1 can be peeled clearly and easily. Note that the peeling layer 2 is removed with the carrier foil 1 together when peeling and removing the carrier foil 1.
On the contrary, on the electrolytic copper plating layer (copper foil) 4 that is attached with the glass epoxy substrate, after placing a through hole and a through hole plating are performed sequentially, an etching process is performed to a copper foil that is in the surface of the copper clad laminate, a wiring pattern 1, having a desired line width and desired pitches of adjacent lines is formed, and finally, forming of a solder resist and other finishing processes are performed.
Since a fine pattern can be formed and handling ability is superior in handling, such a copper foil with a carrier foil, in particular an ultra-thin copper foil of which thickness is very thin obtains an assessment that it is a suitable copper foil when producing a build-up wiring board in particular is obtained. However, meanwhile, the following point at issue is actualized.
The conventional electrolytic copper plating layer 4 is, as shown in FIG. 1, a portion of a salient and a portion of a depression exist on the surface (hereinafter these are defines as a salient of a based material).
When roughening grains 5 are electrodeposited on such a surface, roughening grains are electrodeposited intensively at the portion of a salient and are not electrodeposited aboundingly at the portion of a depression.
A copper foil of such a shape improves peel strength with a resin substrate, whereas is hardly dissolved and causes “treatment transfer after etching”.
Conventionally, in a treatment side deposited such a roughening grain, Rz was around 3.5 mu m, it was limit that a thin line of which line/space was about 30 mu m/30 mu m to 25 mu m/25 mu m was formed, if the surface after roughening treatment was not smooth, it was impossible to form line/space was 15 mu m/15 mu m that is the to be a megatrend of a coming semiconductor package substrate.
Moreover, the surface roughness Rz is a ten point height of roughness profile described in Japanese Industrial Standards B 0601-1994.